Silicon stacked interconnect technology (SSIT) involves packaging multiple integrated circuit (IC) dies into a single package that includes an interposer and a package substrate. Utilizing SSIT expands IC products such as FPGAs into higher density, lower power, greater functionality, and application specific platform solutions with low cost and fast-to-market advantages.
Conventionally, SSIT products are implemented using an interposer that includes an interposer substrate layer with through-silicon-vias (TSVs) and additional metallization layers built on top of the interposer substrate layer. The interposer provides connectivity between the IC dies and the package substrate. However, fabricating the interposer substrate layer with TSVs for the SSIT products is a complex process. This is due to the several fabrication steps necessary to form the interposer substrate layer with the TSVs that include: forming TSVs within the interposer substrate layer, performing backside thinning and chemical vapor deposition (CVD) or chemical mechanical planarization (CMP), and providing thin wafer handling. Thus, forming SSIT products that includes an interposer having an interposer substrate layer with through-silicon-vias (TSVs) may be undesirable for certain applications.